This invention relates to high speed CMOS integrated circuits, and specifically to a method to form a SiGe layer with hydrogen implantation.
In enhanced mobility MOSFET device applications thick, relaxed Si1xe2x88x92xGex buffer layers have been used as virtual substrates for thin strained silicon layers to increase carrier mobility for both nMOS devices Welser et al, Strain dependence of the performance enhancement in strained-Si n-MOSFETs, IEDM Conference Proceedings, p. 373 (1994); Rim et al., Fabrication and analysis of Deep submicron strained-Si N-MOSFETs, IEEE Transactions on Electron Devices, Vol 47, 1406, (2000); and Rim et al, Strained Si NMOSFETs for high performance CMOS technology, 2001 Symposium on VLSI Technology Digest of Technical Papers, p. 59, IEEE 2001; and pMOS devices, Rim et al, Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs, IEDM Conference Proceedings, p. 517 (1995); and Nayak et al, High-mobility Strained-Si PMOSFETs, IEEE Transactions on Electron Devices, Vol. 43, 1709 (1996). Compared with bulk silicon devices, enhancement in electron mobility of 70% for devices with Leff less than 70 nm has been reported by Rim et al., 2001. Enhancements of up to 40% in high-field hole mobility for long-channel devices have also been found by Nayak et al.
Thick Si1xe2x88x92xGex layers relax plastically by the formation of misfit dislocations, R. Hull et al., Nucleation of misfit dislocations in strained-layer epitaxy in the GexSi1xe2x88x92x/Si system, J. Vac Sci. Technol., A7, 2580, 1989; Houghton, Strain relaxation kinetics in Si1xe2x88x92xGex/Si heterostructures, J. Appl. Phys., 70, 2136, 1991; Wickenhauser et al., Determination of the activation energy for the heterogeneous nucleation of misfit dislocations in Si1xe2x88x92x/Gex/Si deposited by selective epitaxy, Appl. Phys. Lett., 70, 324, 1997; Matthews et al., Defects in epitaxial multilayers, J. Cryst. Growth, 27, 118, 1974; and Tang et al., Investigation of dislocations in Si1xe2x88x92xGex/Si heterostructures grown by LPCVD, J. Cryst. Growth, 125, 301, 1992. During this process threading dislocations usually are created. The existence of threading dislocations degrades device performance and reduces device yield significantly.
The current state of the art technique to fabricate a high quality relaxed Si1xe2x88x92xGex buffer layer is the growth of a several xcexcm thick compositionally graded layer Rim et al., 2000; Nayak et al.; Schxc3xa4ffler et al., High-electron-mobility Si/SiGe heterostructures: influence of the relaxed SiGe buffer layer, Semiconductor. Sci. Technol., 7. 260, 1992; and Fitzgerald et al., Totally relaxed GexSi1xe2x88x92x layers with low threading dislocation densities grown on Si substrates, Appl. Phys. Lett., 59, 811, 1991. However, the density of threading dislocations is still high, e.g., typically  greater than 106 cmxe2x88x922. In addition, the integration of a several xcexcum thick Si1xe2x88x92xGex layer into commercial viable device fabrication is not practical. The relaxation of SiGe grown on Separation by IMplantation of Oxygen (SIMOX) wafers has also been investigated, in this case the Si/SiGe bilayer behaves as a free-floating foil constrained to remain flat by the substrate. However, the ratio of thicknesses between the silicon and SiGe layers must be precisely controlled to move the nucleation and glide of dislocations from the SiGe layer to the silicon layer. Also, this technique needs to be extended to include higher Ge content to have utility for most technological applications, LeGouse et al., Relaxation of SiGe thin films grown on Si/SiO2 substrates, J. Appl. Phys. 75 (11) 1994. Powell et al, New approach to the growth of low dislocation relaxed SiGe material, Appl. Phys. Lett., vol. 64, 1856 (1994).
Cavities formed in silicon and Ge and their alloys by helium implantation and annealing were found to have a strong short-range, attractive interaction with dislocations. Introducing cavities at the SiGe/Si interface greatly enhances the relaxation rate and alters dislocation microstructures. However, reduction of threading dislocation density has not been observed, Follstaedt et al., Cavity-dislocation interactions in Si-Ge and implications for heterostructure relaxation, Appl. Phys. Lett., 69, 2059, 1996. To achieve an 80% relaxation, a one hour anneal at about 1000xc2x0 C. is required.
Hydrogen implantation has been reported to induce exfoliation of silicon and cause shearing of macroscopic layers of silicon, Weldon et al, On the mechanism of the hydrogen-induced exfoliation of silicon, J. Vac. Sci. Technol. B. 15, 1065, 1997. This was applied to the fabrication of high-quality silicon-on-insulator (SOI) wafers, and is known as the SmartCut(trademark) process. Recent publications by a German collaboration, S. Mantl et al. and H. Trinkaus et al., have reported the advantages of using hydrogen implantation to increase the degree of SiGe relaxation and to reduce the density of threading dislocation, S. Mantl et al, Strain relaxation of epitaxial SiGe layers on Si(100) improved by hydrogen implantation, Nuclear Instruments and Methods in Physics Research B 147, 29, (1999), and H. Trinkaus et al, Strain relaxation mechanism for hydrogen-implanted Si1xe2x88x92xGex/Si(100) heterostructures, Appl. Phys. Lett., 76, 3552, 2000. However, the researchers reported the relaxation of a SiGe layer having a thickness of only 2000 xc3x85 to 2500 xc3x85, having a Ge concentration, by molecular weight, of less than 22% Ge. SiGe of such thickness is not sufficient for commercial device applications. A method for making thicker films is disclosed in related application Ser. No. 09/541,255, while a method reducing leakage current through proper isolation is disclosed in related application Ser. No. 09/783,817. Related application Ser. No. 09/541,255 describes fabrication of SiGe thin films with about 21% Ge. A higher Ge content is desirable in order to increase the strain in the cap silicon channel and so to farther improve the electron and hole mobility.
The German collaboration has reported that helium implantation is effective in creating highly relaxed SiGe layers with up to 30% Ge, M. Luysberg et al., Relaxation of Si1xe2x88x92xGex buffer layers on Si(100) through Helium implantation, Abstracts of the 2001 MRS Spring Meeting, Abstract P5.4, Apr. 18, 2001. During the oral presentation of that paper, it was specifically reported that 80% relaxation was achieved on a 100 nm thick SiGe layer with 30% Ge content through implantation of 18 keV Helium ions at a dose of 1xc2x71016 cmxe2x88x922 to 3xc2x71016 cmxe2x88x922, and a RTA of 750xc2x0 C. to 1000xc2x0 C. The speaker specifically stated that hydrogen implantation does not work for films with Ge content greater than 22%. In order to produce a smooth, 100 nm to 500 nm thick layer of relaxed SiGe having a Ge content greater than 22%, it was reported that helium implantation is necessary, and that hydrogen implantation does not work.
A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 22%, by molecular weight; implanting H+ ions into the SiGe layer at a dose of between about 1xc2x71016 cmxe2x88x922 to 5xc2x71016 cmxe2x88x922, at an energy of between about 20 keV to 45 keV; thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650xc2x0 C. to 950xc2x0 C. for between about 30 seconds and 30 minutes; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.
The objective of this invention is to produce a thick, e.g., 100 nm to 500 nm, relaxed, smooth SiGe film with high Ge content ( greater than 22%) as a buffer layer for a tensile strained silicon film to be used for high speed MOSFET applications.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.